The present invention concerns a semiconductor memory device, and more particularly a dynamic random access memory (DRAM) having a large capacity.
In the technical field of semiconductor memory devices, there have been many attempts to increase the memory capacity by increasing the number of memory cells on a single chip. In order to achieve such an object, it is important to minimize the area of the memory cell array by forming a plurality of memory cells on a limited surface of the chip, and in view of the minimum area it has been well known that a memory cell consisting of one transistor and one capacitor is desirable. However, since the capacitor occupies most of the area of the memory cell formed by one transistor and one capacitor, it is important that though the area occupied by the capacitor is minimized, the capacitance thereof is increased so that the data reading operation is facilitated and the soft errors due to the alpha .alpha. particle are reduced.
In order to resolve the above problem, there have been proposed several methods for forming capacitors having trenches on the surface of a semiconductor substrate so that the area occupied by the capacitor is minimized and the capacitance of the capacitor is maximized. In fact, it is necessary to employ the trench type construction in a DRAM having storage capacity more than four mega-bits.
An example of the memory cell employing a conventional trench construction is disclosed in pages 272-273 of ISSCC Digest of Technical Papers issued February, 1986.
Because the above memory cell has a cell plate of polysilicon formed on the upper surface of the substrate, the plate connection is difficult in a memory cell with a large integration of more than 16 kilo-bits, and the cell plate of polysilicon may easily produce the step coverage which causes a stringer to be produced. Furthermore, as the above memory cell stores the charge outside the trench, soft errors may easily occur.
On the other hand, in the stacked memory cell with cell plates formed on the word lines, the problem inherent in the above memory cell due to the plate may be resolved. However, if the trenches are formed in large integration, the two adjacent trenches are separated from each other by a thick field oxide layer, so that the lower part of the field oxide layer can not be effectively employed. Therefore, the degree of integration can not be increased.
An U.S. patent application Ser. No. 000743 filed on Oct. 16, 1987 and now abandoned, discloses a memory cell to solve the problems inherent in the above two types of memory cells. In the memory cell of the U.S. patent application No. 000743, since the cell plate formed in the substrate has the same potential as the substrate, to the cell plates cannot be independently applied a voltage different from that of the substrate.